1. Field of the Invention
The invention relates to an insulated gate-type semiconductor device and a method of manufacturing the same, specifically to an insulated gate-type semiconductor device with improved step coverage of a source electrode and a manufacturing method thereof.
With insulated gate-type semiconductor devices like a MOSFET, the cell density is improved to achieve a low on resistance by using a trench structure.
2. Description of the Related Art
FIG. 9 shows an example of an N-channel type power MOSFET structure with a conventional trench structure. A drain region 21b is provided, for instance by laminating an N−-type epitaxial layer on an N+-type silicon semiconductor substrate 21a. A P-type channel layer 24 is formed on a surface of the drain region 21b. A trench 27 is provided which penetrates the channel layer 24 to reach the drain region 21b and inner walls thereof are covered with a gate oxide film 31. Further, the trench 27 is filled with polysilicon, for instance, to form a gate electrode 33.
An N+-type source region 35 is formed on a surface of the channel layer 24 adjacent the trench 27 and a P+-type body region 34 is provided on a surface of the channel layer 24 between adjacent source regions 35 of two cells. A channel region (not illustrated) is formed in the channel layer 24, from the source region 35 and along the trench 27. The gate electrode 33 is covered with an interlayer dielectric film 36 and a source electrode 37 is provided which is in contact with the source region 35 and the body region 34.
FIGS. 10 through 14 show a manufacturing method of a power MOSFET having a conventional trench structure.
As shown in FIG. 10, a semiconductor substrate 21 is prepared by laminating an N−-type epitaxial layer 21b forming a drain region on an N+-type silicon semiconductor substrate 21a. After boron is doped and diffused in a surface of the substrate 21, a P-type channel layer 24 having a thickness of about 1.5 μm is formed.
Then, a trench 27 having a depth of around 2.0 μm is formed by anisotropically dry etching the substrate 21 with a CF and an HBr group gas while using a CVD oxide film as a mask (not shown here) and penetrating the channel layer 24 to reach the drain region 21b. The entire surface is subjected to thermal oxidation and a gate oxide layer 31 of around 700 Å is formed on inner walls of the trench 27.
A gate electrode 33 filling the trench 27 is formed as shown in FIG. 11 by depositing a non-doped polysilicon layer (not shown) to the entire surface, implanting and diffusing high-concentration impurities to obtain a high specific conductivity. Next, the polysilicon layer deposited to the entire surface is dry etched without using a mask, leaving the gate electrode 33 filled in the trench 27.
In FIG. 12, boron is selectively ion implanted in doses of around 5.0×1014 cm−2 using a mask formed of a resist film (not shown here) to remove the resist film. After under going a process of annealing, a P+-type body region 34 is formed.
As in FIG. 13, a mask is provided on the surface so that the source region 35 to be formed later and the gate electrode 33 are exposed and the arsenic (As) is implanted in doses of 5.0×1015 cm−2 then the resist film is removed. After undergoing a process of annealing, an N+-type source region 35 is formed on a surface of the channel layer 24 adjacent the trench 27.
After a TEOS (Tetra Ethyl Ortho Silicate) film (not shown) of about 2000 Å is provided on the entire surface as illustrated in FIG. 14, a BPSG (Boron Phosphorus Silicate Glass) layer of about 6000 Å is deposited by the CVD method. A resist layer PR is masked so that it is left at least on the gate electrode 33 to thus form an interlayer dielectric film 36 and the resist layer PR is removed. In the next step, aluminum is sputtered to the entire surface in a sputtering apparatus to form a source electrode 37 which contacts the source region 35 and the body region 34 (Refer to FIG. 9). This technology is described for instance in Japanese Patent Application Publication No. 2001-274396.
The above conventional device comprises an interlayer dielectric film 36 for insulating the gate electrode 33 and the source electrode 37. Because the interlayer dielectric film 36 may have a thickness of about 8000 Å, the step coverage of the source electrode 37 formed by sputtering deteriorates and a void 50 as shown in FIG. 15 may be formed. The void 50 causes an increase in the wiring resistance and becomes a characteristic deteriorating factor. Also, stresses are applied to the corner of the interlayer dielectric film 36 at the time of the source electrode 37 wire bonding and molding and cracks 51 may occur starting from the interlayer dielectric film 36 to the silicon substrate 21.
Also, the problem occurring in the conventional process is that when a predetermined body region is not secured, the avalanche resistance and parasitic operation between the body region 34 and the source region 35 deteriorate. Moreover, because of placement error of mask to form the interlayer dielectric film 36 that prevents short circuit between the gate electrode 33 and the source electrode 37, the interlayer dielectric film 36 is formed to have a larger size than the width of the trench 27.
On the one hand, as the miniaturization of device advances, the area of the source region 35 is further reduced and so is the contact area between the source region 35 and the source electrode 37.
Conventionally, one mask is used in the formation of each of the source region 35, body region 34 and interlayer dielectric film 36. Accordingly, because of the placement errors of the masks to form the interlayer dielectric film 36, the body region 34 and the source regions 35, the sufficient contact area between the source region 35 and the source electrode 37 cannot be secured, thus causing an increase in the wiring resistance of the source electrode.